CHIP_SASEBO_W_VCP Project Status (01/24/2013 - 01:21:53)
Project File: sasebo-w-unified-iseproject.xise Parser Errors: No Errors
Module Name: CHIP_SASEBO_W_VCP Implementation State: Programming File Generated
Target Device: xc6slx150-2fgg484
  • Errors:
No Errors
Product Version:ISE 14.4
  • Warnings:
89 Warnings (2 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 749 184,304 1%  
    Number used as Flip Flops 749      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 710 92,152 1%  
    Number used as logic 677 92,152 1%  
        Number using O6 output only 298      
        Number using O5 output only 134      
        Number using O5 and O6 245      
        Number used as ROM 0      
    Number used as Memory 0 21,680 0%  
    Number used exclusively as route-thrus 33      
        Number with same-slice register load 26      
        Number with same-slice carry load 7      
        Number with other load 0      
Number of occupied Slices 302 23,038 1%  
Number of MUXCYs used 300 46,076 1%  
Number of LUT Flip Flop pairs used 914      
    Number with an unused Flip Flop 291 914 31%  
    Number with an unused LUT 204 914 22%  
    Number of fully used LUT-FF pairs 419 914 45%  
    Number of unique control sets 48      
    Number of slice register sites lost
        to control set restrictions
179 184,304 1%  
Number of bonded IOBs 60 338 17%  
    Number of LOCed IOBs 60 60 100%  
    IOB Flip Flops 4      
Number of RAMB16BWERs 32 268 11%  
Number of RAMB8BWERs 0 536 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 9 16 56%  
    Number used as BUFGs 8      
    Number used as BUFGMUX 1      
Number of DCM/DCM_CLKGENs 1 12 8%  
    Number used as DCMs 1      
    Number used as DCM_CLKGENs 0      
Number of ILOGIC2/ISERDES2s 1 586 1%  
    Number used as ILOGIC2s 1      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 586 0%  
Number of OLOGIC2/OSERDES2s 3 586 1%  
    Number used as OLOGIC2s 3      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 384 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 180 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 4 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 6 16%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 4.25      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Jan 24 01:19:38 2013079 Warnings (0 new)36 Infos (0 new)
Translation ReportCurrentThu Jan 24 01:19:45 2013005 Infos (0 new)
Map ReportCurrentThu Jan 24 01:20:20 201302 Warnings (0 new)8 Infos (2 new)
Place and Route ReportCurrentThu Jan 24 01:20:55 201308 Warnings (2 new)0
Power Report     
Post-PAR Static Timing ReportCurrentThu Jan 24 01:21:07 2013003 Infos (0 new)
Bitgen ReportCurrentThu Jan 24 01:21:32 2013001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentThu Jan 24 01:21:33 2013
WebTalk Log FileCurrentThu Jan 24 01:21:52 2013

Date Generated: 01/24/2013 - 01:21:53