interface Project Status (01/23/2013 - 11:54:08)
Project File: avnet_lx9board_ise.xise Parser Errors: No Errors
Module Name: interface Implementation State: Programming File Generated
Target Device: xc6slx9-2csg324
  • Errors:
No Errors
Product Version:ISE 14.4
  • Warnings:
114 Warnings (23 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 787 11,440 6%  
    Number used as Flip Flops 787      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 818 5,720 14%  
    Number used as logic 782 5,720 13%  
        Number using O6 output only 439      
        Number using O5 output only 144      
        Number using O5 and O6 199      
        Number used as ROM 0      
    Number used as Memory 1 1,440 1%  
        Number used as Dual Port RAM 0      
        Number used as Single Port RAM 0      
        Number used as Shift Register 1      
            Number using O6 output only 1      
            Number using O5 output only 0      
            Number using O5 and O6 0      
    Number used exclusively as route-thrus 35      
        Number with same-slice register load 28      
        Number with same-slice carry load 6      
        Number with other load 1      
Number of occupied Slices 293 1,430 20%  
Number of MUXCYs used 332 2,860 11%  
Number of LUT Flip Flop pairs used 967      
    Number with an unused Flip Flop 252 967 26%  
    Number with an unused LUT 149 967 15%  
    Number of fully used LUT-FF pairs 566 967 58%  
    Number of unique control sets 50      
    Number of slice register sites lost
        to control set restrictions
172 11,440 1%  
Number of bonded IOBs 68 200 34%  
    Number of LOCed IOBs 68 68 100%  
    IOB Flip Flops 1      
Number of RAMB16BWERs 16 32 50%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 6 16 37%  
    Number used as BUFGs 5      
    Number used as BUFGMUX 1      
Number of DCM/DCM_CLKGENs 2 4 50%  
    Number used as DCMs 2      
    Number used as DCM_CLKGENs 0      
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 1 200 1%  
    Number used as OLOGIC2s 1      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.96      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Jan 23 23:15:59 2013074 Warnings (0 new)29 Infos (0 new)
Translation ReportCurrentWed Jan 23 23:16:07 201302 Warnings (0 new)2 Infos (0 new)
Map ReportCurrentWed Jan 23 23:16:27 2013022 Warnings (20 new)8 Infos (2 new)
Place and Route ReportCurrentWed Jan 23 23:16:40 2013015 Warnings (3 new)0
Power Report     
Post-PAR Static Timing ReportCurrentWed Jan 23 23:16:46 2013003 Infos (0 new)
Bitgen ReportCurrentWed Jan 23 23:16:58 201301 Warning (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentWed Jan 23 23:16:58 2013
WebTalk Log FileCurrentWed Jan 23 23:17:18 2013

Date Generated: 01/24/2013 - 21:12:39